
#ifndef   ___SYSTEM__H__
#define   ___SYSTEM__H__

#include "LPC_UTIL_DEFS.h" 

#define   USE_USB		1

#define   TARGET_FREQ		(18000000)

#define FOSC            (12000000)  // Master Oscillator Freq.
#define PLL_MUL         (12)        // PLL Multiplier 
#define PLL_DIV         (1)         // PLL Divider
#define FCCO          	(FOSC*PLL_MUL*2/PLL_DIV) // CC Osc. Freq. 12*12*2=288MHz
#define CCLK_DIV        (FCCO/TARGET_FREQ)         // PLL out -> CPU clock divider 288/18 = 16
#define USBCLK_DIV		(1) 
#define CCLK         	( FCCO / CCLK_DIV ) // CPU Clock Freq.    288/16=18MHz


// Pheripheral Bus Speed Divider
#define PBSD                1           // MUST BE 1, 2, or 4
#define PCLK                (CCLK / PBSD) // Pheripheal Bus Clock Freq.

// Do some value range testing
// TODO: check minimum for LPC23xx/24xx
#if ((FOSC < 10000000) || (FOSC > 25000000))
#error Fosc out of range (10MHz-25MHz)
#error correct and recompile
#endif

#if ((CCLK < 10000000) || (CCLK > 72000000))
// TODO: check minimum for LPC23xx/24xx
#error cclk out of range (10MHz-72MHz)
#error correct PLL_MUL and recompile
#endif

// "The resulting frequency must be in the range of 275 MHz to
// 550 MHz." (Manual p. 36)
#if ((FCCO < 275000000) || (FCCO > 550000000))
#error Fcco out of range (275MHz-550MHz)
#error internal algorithm error
#endif

#if ((PBSD != 1) && (PBSD != 2) && (PBSD != 4))
#error Pheripheal Bus Speed Divider (PBSD) illegal value (1, 2, or 4)
#endif

void interrupts_enable( void );
void interrupts_disable( void );
void cpu_restore_sr(int);
int  cpu_save_sr(void);

void sysInit( void );

void  cpu_irq_isr(void);
void  cpu_fiq_isr(void);

void wdt_reload (void );
void wdt_init( unsigned int Timeout );
void sys_reset ( void );

/* #if USE_USB		/\* 1 is USB, 0 is non-USB related *\/   */
/* /\* Fcck = 57.6Mhz, Fosc = 288Mhz, and USB 48Mhz *\/ */
/* #define PLL_MValue			11 */
/* #define PLL_NValue			0 */
/* #define CCLKDivValue			4 */
/* #define USBCLKDivValue		5 */

/* /\* System configuration: Fosc, Fcclk, Fcco, Fpclk must be defined *\/ */
/* /\* PLL input Crystal frequence range 4KHz~20MHz. *\/ */
/* #define Fosc	12000000 */
/* /\* System frequence,should be less than 80MHz. *\/ */
/* #define Fcclk	57600000 */
/* #define Fcco	288000000 */
/* #else */

/* /\* Fcck = 50Mhz, Fosc = 300Mhz, and USB 48Mhz *\/ */
/* #define PLL_MValue			24 */
/* #define PLL_NValue			1 */
/* #define CCLKDivValue			5 */
/* #define USBCLKDivValue		6 */

/* /\* System configuration: Fosc, Fcclk, Fcco, Fpclk must be defined *\/ */
/* /\* PLL input Crystal frequence range 4KHz~20MHz. *\/ */
/* #define Fosc	12000000 */
/* /\* System frequence,should be less than 80MHz. *\/ */
/* #define Fcclk	50000000 */
/* #define Fcco	300000000 */

/* #endif */

/* /\* APB clock frequence , must be 1/2/4 multiples of ( Fcclk/4 ). *\/ */
/* /\* If USB is enabled, the minimum APB must be greater than 16Mhz *\/  */
/* #if USE_USB */
/* #define Fpclk	(Fcclk / 2) */
/* #else */
/* #define Fpclk	(Fcclk / 4) */
/* #endif */

#endif
